1. Field of the Invention
The present invention relates to a method of piping defect detection, and more particularly, to a fast and sensitive method of piping defect detection.
2. Description of the Prior Art
In the semiconductor fabricating process, after electric devices, such as MOS transistors, are formed in a substrate, a dielectric layer, which is a so-called inter layer dielectric layer, is typically formed thereon for isolating and protecting the electric devices beneath. Normally, a plurality of contact holes are disposed in the inter layer dielectric layer for filling a conductive layer which is used to form a contact plug in each of the contact holes. Thus, the electric devices can electrically connect with other external electric devices, such as a conductive wire, through the contact plugs. Hence, data signals can be transferred to the electric devices, such as a source or drain of a transistor, through the conductive wire and the contact plug to control the operation of each electric device.
A DRAM wafer is illustrated in the following to describe a fabricating method of the contact plug in the prior art. Please refer to FIG. 1 and FIG. 2, which are schematic diagrams of a method of forming an electric connection through contact plugs. As shown in FIG. 1, a wafer 10 comprises a substrate 12, and transistors 14, 16, 18, and 20 disposed on the surface of the substrate 12. The transistor 14 uses the same silicon layer as its gate with the transistor 18 and the same doped region as its source with the transistor 16. In the same manner, the transistor 20 shares a polysilicon layer with the transistor 16 and a source with transistor 18. As shown in FIG. 2, a dielectric layer 22, such as a borophospho-tetra-ehtyl-ortho silicate (BPTEOS) layer, is deposited on the wafer 10. Then a photo-etching process is used to form a plurality of contact holes in the dielectric layer 22. After that, a conductive layer (not shown), such as a polysilicon layer, is deposited on the dielectric layer 22 to fill the contact holes for forming contact plugs 26, 28, 30, 32, 34, and 36.
As the process size shrinks and the integration of device increases, when the dielectric layer 22 is deposited, a plurality of voids 24 with piping shapes are easily formed among gates due to the low filling ability of the dielectric layer 22. Thus, some contact holes connect with each other. Although a rapid heat treatment is often used to perform a reflow process for reducing the voids 24, the presence of voids 24 can not be prevented in most cases. Therefore, in the following process of contact plug formation, some contact plugs will connect with or short each other, such as the contact plugs 34 and 36 shown in FIG. 2, that cause the transistors 14, 16, 18, and 20 to not operate properly. It is a so-called piping defect.
For clarity, the wafer 10 is illustrated as a detected sample to describe the conventional method of piping defect detection. Please refer to FIG. 3, which is a schematic diagram of the method of piping defect detection in the prior art. The piping defects often appear in a distance under the surface of the dielectric layer 22. Thus, a proper pretreatment is required for the sample before performing the defect inspection. As shown in FIG. 3, in the conventional method of piping defect detection, after sampling 50, a chemical mechanic polish (CMP) process 60 is performed to remove layers on the dielectric layer, such as a polysilicon layer for forming the contact plug. Then, a wet etching process 70 is used to remove parts of the dielectric layer 22. After that, a defect inspection 80 is performed with a scanning electron microscope (SEM). According to the result of the defect inspection 80, a failure bit map (FBM) can be made to analyze the root cause of piping defects in advance for reducing the generation of voids 24 by adjusting the fabricating process parameters properly.
However, the defect inspection 80, which is the last step of the piping defect detection in the prior art, must be manually inspected by engineers, which requires a lot of time and effort. For example, it normally takes more than 12 hours to inspect a batch of 50 samples. When any problem appears in the deposition of the dielectric layer 22, it will be detected or found in the wafer test performed two months latter. It is obvious that engineers have to spend more time in the process parameter tuning to find a proper process margin of the deposition process. In addition, since the piping defects are very small, normally with a size below 0.1 xcexcm for a DRAM of 0.13 xcexcm process, it is too hard for engineers to examine the wafer in a large scale inspection. Moreover, engineers often make careless mistakes while examining the wafer and do not notice the presence of the piping defects. This leads to serious problems in the following root cause analysis process. Thus, process parameters cannot be adjusted properly and efficiently and the reliability of the products is thereby deteriorated.
Along with the promotion of the semiconductor fabricating process and the scaling-up due to economic reasons, the diameter of semiconductor wafers is increasing from 8 inches to 12 inches, and the line width is also shrinking from 0.18 xcexcm to 0.13 xcexcm, and even to 0.1 xcexcm. During the time of great process updates, a high level of experience and testing is required to confirm the margins of each process parameter so that the reliability of products can be maintained during mass production. It is obvious that the conventional technology cannot meet the requirement. Conventional technology always requires a lot of time and cost, but the correct process margins of parameters are still not obtained. Thus, a fast and sensitive method of defect detection is required to solve aforementioned problems.
It is therefore a primary objective of the claimed invention to provide a fast and sensitive method of piping defect detection to solve the aforementioned problems in the prior art.
In a preferred embodiment of the claimed invention, a sample is first proved. The sample comprises a silicon substrate, a plurality of electric devices disposed thereon, a dielectric layer covering the plurality of electric devices and the silicon substrate, and a polysilicon layer formed on the dielectric layer electrically connected to the electric devices through contact holes in the dielectric layer. A chemical mechanic polishing process is performed to remove the polysilicon layer and parts of the dielectric layer of the sample. Then, a wet etching process is performed to remove parts of the dielectric layer. After that, the sample is inspected under an ultraviolet light irradiation for detecting the piping defects in the dielectric layer of the sample.
It is an advantage of the claimed invention that since the defects can be detected under the UV light irradiation according to the brightness contrast between the polysilicon layer and the silicon oxide layer after a CMP process and a wet etching process are used to pretreat the sample, a real-time automatic defect classification (ADC) tool can be applied to detect the online samples. Thus, the yield and reliability of products can be improved effectively.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.